Generally, integrated circuit memory devices can be classified into volatile memory devices and nonvolatile memory devices. The volatile memory devices lose stored data when power is removed, whereas the nonvolatile memory devices still maintain stored data even when power is removed.
Flash memory devices are one kind of the nonvolatile memory devices and are high-integration devices that may combine aspects of an erasable programmable read only memory (EPROM) which can be programmed and erased, with aspects of an electrically erasable programmable read only memory (EEPROM) which can be electrically programmed and erased.
The flash memory devices may be classified into floating gate type flash memory devices and charge trap type flash memory devices depending on the kind of charge storage layer that constitutes a unit cell. Also, the flash memory devices may be classified into stacked gate type flash memory devices and split gate type flash memory devices depending on a unit cell structure.
Also, the flash memory devices can be classified into NOR type flash memory devices and NAND type flash memory devices. Since the NOR type flash memory device can control the respective memory cells independently, it can provide relatively high speed operation. However, the NOR type flash memory device may have a relatively large cell area because it may need one contact per two cells. On the other hand, since the NAND type flash memory can integrally control a plurality of memory cells connected to one string, it may provide a relatively high integration density.
FIG. 1 is a partial equivalent circuit diagram of a conventional general memory device, and FIG. 2 is a plan view of a conventional general NAND memory device.
Referring to FIG. 1, a NAND flash memory device includes a cell array comprised of a plurality of cell strings. Each cell string includes a ground select transistor and a string select transistor connected in series between a source region and a drain region, and a plurality of memory cells connected in series between the ground select transistor and the string select transistor. The cell array includes a plurality of ground select lines GSL and a plurality of string select lines SSL, and a plurality of word lines WL disposed between a string select line SSL and a ground select line GSL. Also, bit lines BL intersecting the plurality of word lines are provided. Each bit line is connected to the drain region through a bit line contact DC. A common source line CSL is disposed between the ground select lines GSL. The source regions are electrically connected to one another by the common source line CSL.
Referring to FIG. 2, active regions 12 are defined by a device isolation layer 15 formed in a substrate such as a semiconductor substrate. The active regions 12 extend in a first direction DA. The ground select lines GSL, string select lines SSL and word lines WL are disposed crossing over the active regions 12. The word lines WL and the select lines GSL and SSL extend in a second direction DW orthogonal to the first direction DA. The common source line CSL crossing over the active regions and electrically connected to the underlying active regions is disposed between the ground select lines GSL of the cell strings adjacent to each other, and bit line contacts DC are connected to the active regions between the adjacent string select lines SSL and are also connected to the bit lines (not shown) crossing over the word lines WL. Floating gates 24, serving as charge storage regions, are disposed on regions where the active regions and the word lines WL cross. The floating gates 24 are positioned between the active regions 12 and the word lines WL. When the width of the active region 12, the width of the word line WL, the width between the active regions 12 and the width between the word lines are all equal to ‘a’, a floating gate positioned at a center is adjacent to two floating gates spaced apart by the distance ‘a’ in the first direction DA, and adjacent to two floating gates spaced apart by the distance ‘a’ in the second direction DW, and adjacent four floating gates spaced apart by the distance √{square root over (2)}a in the diagonal directions.
As the memory device becomes more highly integrated, the parasitic capacitance between the floating gates may increase and thus a malfunction of the memory device, e.g., a program disturbance between memory cells, may be caused.
FIG. 3 is a partial perspective view of a memory device for illustrating a relationship between the floating gate voltage and the parasitic capacitance.
Referring to FIG. 3, a gate structure 20, in which a tunnel oxide layer 22, a floating gate 24, an insulating layer such as an ONO layer 26, and a control gate 28 are sequentially stacked, is formed on an active region 12 defined by a device isolation layer 15 formed in a substrate 10. The active region 12 extends in a first direction DA, and the control gate 28 extends in a second direction DW to constitute a word line. An interlayer insulating layer (not shown) is positioned between the adjacent gate structures in the first direction DA.
Reference symbols V and C marked on the drawing represent voltage and capacitance in a corresponding position. Vfg indicates a voltage of the floating gate positioned at a center among nine floating gates that are illustrated. VA indicates a voltage of the floating gates adjacent to the center floating gate in the first direction DA, and VW indicates a voltage of the floating gates adjacent to the center floating gate in the second direction DW. Also, Cfgw indicates a parasitic capacitance generated between the floating gates adjacent in the second direction DW.
A word line made of a conductive layer is interposed between two adjacent floating gates in the second direction DW, which can reduce or suppress a parasitic capacitance Cfgw from being generated. However, since only the interlayer insulating layer is positioned between two adjacent floating gates in the first direction, the generation of the parasitic capacitance Cfgw may not be effectively suppressed. In other words, a floating gate may have a larger electrical interference due to the adjacent floating gates in the first direction DA rather than the adjacent floating gates in the second direction DW. As a result, the reliability and/or operation characteristics may be deteriorated.